Computer science University of Haifa.
My research is mainly about the problem of hardware-software co-synthesis and FPGA acceleration of programs.
I study efficient ways to
compile from high-level languages ( C,C++,Java) to Verilog or even directly to ASIC.
I am using different graph cover algorithms C(G)
as the main engine for my highlevel synthesis tools as a way to improve the resulting circuit (reduced wire
lengths and reduced MUX complexity ...). I work with the LLVM compiler converting LLVM byte code to graphs of operations
or algebraic circuits (G). Applying various graph cover algorithms to these Gs
allow efficient synthesis to circuits.
I am also studying the following problems:
- Compilation of boolean circuits to non deterministic branching programs (no size blowup) as way to synthesize circuits of Optical switching devices and Ballistic Deflection Transistors.
- Parallel CPU architectures for embedded systems and SOCs. The goal is to develop 1K many core shared memory architecture that consume less than five Watts so that SOCs can be developed as pure parallel programs.
- Developing pracical models of the reconfigurable mesh (RM) and developing an FPGA architecture that is based on the RM model.
Research Interests
- Compilers
- High-level Synthesis
- Reconfigurable networks
- Embedded systems
- Parallel architectures
- Parallel Programming
Contact Info
Email: yosi at cs dot haifa dot ac dot il.
Phone: 972-4-8240338