I am an academic researcher giving consulting services to the Industry in the area of compiler construction
And high level synthesis to Verilog including:
- Developing new optimizations for existing compilers.
- Adapting known optimizations to specific hardware/CPU features.
- Porting existing compilers to specific CPU architectures.
- Guiding teams, short courses, development programs.
- Special emphasis on DSP, loop transformations, prefetching, list-scheduling, modulo scheduling and predication.
- Hardware compilation and high-level synthesis (to VERILOG level only).
- Scheduling techniques: VLIW, Superscalar, list scheduling, modulo scheduling and global scheduling (both for hardware and CPUs)
- Memory optimizations.
- Knowledge in OS and CPU architectures.
to my homepage
- Experience: Starcore Company (2 years) consulting.
- Current research systems: A compiler from high-level languages to VERILOG,
Source level modulo scheduling, ParC a compiler for shared memory parallel
dialect of C, a GCC extension to VLIW scheduling and the DOL compiler
of loops to boolean circuits.
- Work format: one day a week, or a half year sabbatical.