Yosi Ben Asher picture

Computer science University of Haifa.

My research is mainly about the problem of hardware-software co-synthesis and FPGA acceleration of programs. I study efficient ways to compile from high-level languages ( C,C++,Java) to Verilog or even directly to ASIC. I am using different graph cover algorithms C(G) as the main engine for my highlevel synthesis tools as a way to improve the resulting circuit (reduced wire lengths and reduced MUX complexity ...). I work with the LLVM compiler converting LLVM byte code to graphs of operations or algebraic circuits (G). Applying various graph cover algorithms to these Gs allow efficient synthesis to circuits.
I am also studying the following problems:

Research Interests

Contact Info

Email: yosi at cs dot haifa dot ac dot il.

Phone: 972-4-8240338

Compiling programs to circuits: forms the main type of systems I am developing (usually with LLVM). In general, my research is motivated by questions like: boolean-gates versus branching programs, fast probabilistic evaluation of boolean circuits, and optimized time/area tradeoffs in logic synthesis.

Current Research efforts