Proj 2010 SM+Multi-core

  • Psudo C-code as to how to create a butterfly network

    First Part the shared memory module must be submitted till 30 November (a panelty of -4pts from the final grade):

    specifications and initial modules:

  • Switch+Butterfly from 2008
  • Test Module from 2008
  • butterfly network slides

    Shared memory Project: a Verilog module + test bench that implements multiport memory module that can support concurrent read/write operations to a set of memory modules acting as a shared memory. We have discussed this sub-project in class so the main concepts involved with this project are known from the class and hence what follows is just a short list of requirements. You are given an existing multi-stage design from 2008 that you should modify such that:

    NOTE-1: the current sizes of the BF network have been reduced to k=2 and lvls=3 so that it will pass synthesis quickly

    SECOND part: CONNECT SEVERAL CORES with the shared memory module created in the first part

    In this part we create a small multicore system by connecting several cores to the shared memory created in the first part.