//		k	= main parameter:
//		Packet: Module Address(k bits) + Internal Address(2k bits) + R/W(1 bit) + Data(k^2 bits) + Return Address (k bits)
//		R/W flag: 1 - Read, 0 - Write.
// 	entire packet size: k*k + 4k + 1
//		Stops: 0 ok, 1 Stop
//		Connections: Left Side of module = 0, Right side of module = 1
`timescale 1ns/1ps
`define Zero 0
`define One 1



module BF_Switch(Pl,Pr,SPl,SPr,Clock,Ol,Or,SOl,SOr);
	parameter 	k = 2;
	parameter 	i = 0;
	parameter 	p_size = k*k + 4*k + 1;
	parameter 	Pr_size = k;
	parameter 	Mod_size = k;
	parameter 	Intr_size = 2*k;
	parameter	Data_size = k*k;
	
	input 		[p_size-1:0]	 	Pl			, 	Pr;
	input 								SPl		,	SPr		,	Clock;
	output 		[p_size-1:0]	 	Ol			,	Or;
	output 								SOl		,	SOr;
		
	reg 			[p_size-1:0]	 	Ol				,	Or;
	reg 									SOl			,	SOr;
	
	//Packet parts: (internal Variables)
	wire			[Mod_size-1:0]		L_Mod_Add	;	
	wire			[Mod_size-1:0]		R_Mod_Add	;

	reg 									Pref; // sets the preference to change every cycle
	
	//Break Packet to Parts:
	assign L_Mod_Add 	= Pl[p_size-1:Data_size+Intr_size+Pr_size+1];
	assign R_Mod_Add 	= Pr[p_size-1:Data_size+Intr_size+Pr_size+1];
	
	initial begin
		SOl = 0;
		SOr = 0;
		Pref = 1;
	end
	
	always @ (posedge Clock) begin
			
			Pref = ~Pref;
			
			if ((SPl == 1) & (SPr == 1)) begin	// All stop
				SOl = 1;
				SOr = 1;
			end
			else if ((SPl == 0) & (SPr == 0) & (R_Mod_Add[k-1-i] == 1) & (L_Mod_Add[k-1-i] == 0)) begin	// Straight connection
				Or = Pr;
				Ol = Pl;
				SOl = 0;
				SOr = 0;
			end
			else if ((SPl == 0) & (SPr == 0) & (R_Mod_Add[k-1-i] == 0) & (L_Mod_Add[k-1-i] == 1)) begin // Cross connection
				Or = Pl;
				Ol = Pr;
				SOl = 0;
				SOr = 0;
			end
			else if ((SPl == 0) & (SPr == 0) & (R_Mod_Add[k-1-i] == 0) & (L_Mod_Add[k-1-i] == 0)) begin	// left clash (both go left)
				if (Pref == 1) begin
					Ol = Pl;
					SOl = 0;
					SOr = 1;
				end
				else if (Pref == 0) begin
					Ol = Pr;
					SOl = 1;
					SOr = 0;
				end
			end
			else if ((SPl == 0) & (SPr == 0) & (R_Mod_Add[k-1-i] == 1) & (L_Mod_Add[k-1-i] == 1)) begin	// right clash (both go right)
				if (Pref == 1) begin
					Or = Pr;
					SOl = 1;
					SOr = 0;
				end
				else if (Pref == 0) begin
					Or = Pl;
					SOl = 0;
					SOr = 1;
				end
			end
			else if ((SPl == 0) & (SPr == 1) & (L_Mod_Add[k-1-i] == 0)) begin // Left straight connection, Right Stop
				Ol = Pl;
				SOl = 0;
				SOr = 1;
			end
			else if ((SPl == 1) & (SPr == 0) & (R_Mod_Add[k-1-i] == 1)) begin // Right straight connection, left Stop
				Or = Pr;
				SOl = 1;
				SOr = 0;
			end
			else if ((SPl == 0) & (SPr == 1) & (L_Mod_Add[k-1-i] == 1)) begin	// left cross connection, right stop
				SOl = 1;
				SOr = 1;
			end
			else if ((SPl == 1) & (SPr == 0) & (R_Mod_Add[k-1-i] == 0)) begin	// right cross connection, left stop
				SOl = 1;
				SOr = 1;
			end
						
	end
	
endmodule

module BF_Network(INPUTA,INPUTSA,Clock,OUTPUTA,OUTPUTSA);
	parameter k = 2; // k == SIZE (2-> 2x2)
	parameter levels = 2;
	parameter p_size = k*k + 4*k + 1;
	parameter n = 2**k; //number of "Fleets"
	
	
	input [(2*k*p_size)-1:0] 	INPUTA;
	input [(2*k)-1:0]			 	INPUTSA;
	input Clock;
	output [(2*k*p_size)-1:0] 	OUTPUTA;
	output [(2*k)-1:0]			OUTPUTSA;
	
	wire [(2*k*p_size)-1:0] 	OUTPUTA;
	wire [(2*k)-1:0]			OUTPUTSA;
	
	wire [p_size-1:0]		Datawires	[levels:0][(2*k)-1:0];
	wire [0:0]				Stopwires	[levels:0][(2*k)-1:0];
	
	// Assign input and output to data and stop wires
	genvar a;
	generate for (a=0; a<2*k; a=a+1) 
		begin:Assign_INPUTs
			assign Datawires[0][a] = INPUTA[((a+1)*(p_size))-1:(a*p_size)];	// Input Data to wire matrix
			assign Stopwires[levels][a] = INPUTSA[a];	// Input Stops to wire matrix			
			assign OUTPUTA[(a+1)*(p_size)-1:(a*p_size)] = Datawires[levels][a];	// wires to output data
			assign OUTPUTSA[a] = Stopwires[0][a]; 	// wire to output stop		
		end
	endgenerate

	genvar x,y,z,w;
	generate for (x=0; x<2*k; x=x+2)  //genfor for creating first levels (straight)
		begin:Gen_Level_0
			// module BF_Switch(Pl,Pr,SPl,SPr,Clock,Ol,Or,SOl,SOr);
			BF_Switch #(k,0)	sw(.Pl(Datawires[0][x]),
										.Pr(Datawires[0][x+1]),
										.SPl(Stopwires[1][x]),
										.SPr(Stopwires[1][x+1]),
										.Clock(Clock),
										.Ol(Datawires[1][x]),
										.Or(Datawires[1][x+1]),
										.SOl(Stopwires[0][x]),
										.SOr(Stopwires[0][x+1])	);
		end
	endgenerate

	generate for (x=1; x<levels; x=x+1)  //genfor for creating levels
		begin:Gen_Levels
		
		for (y=0; y<k; y=y+2**x) //jumping over 2*fleets
			begin:Jump_Over_Fleets
			
			for (z=y; z<y+2**(x-1); z=z+1) 
				begin:Build_EVEN_Fleets //building EVEN fleets only
				//generate module BF_Switch(Pl,Pr,SPl,SPr,Clock,Ol,Or,SOl,SOr);
				BF_Switch #(k,x)	sw(.Pl(Datawires[x][2*z+1]),
											.Pr(Datawires[x][(2**x)+2*z+1]),
											.SPl(Stopwires[x+1][2**x+2*z]),
											.SPr(Stopwires[x+1][2**x+2*z+1]),
											.Clock(Clock),
											.Ol(Datawires[x+1][2**x+2*z]),
											.Or(Datawires[x+1][2**x+2*z+1]),
											.SOl(Stopwires[x][2*z+1]),
											.SOr(Stopwires[x][(2**x)+2*z+1])	);
											
				end
			for (w=y+2**(x-1); w<y+2**x; w=w+1) 
				begin:Build_ODD_Fleets //building ODD fleets only
				//generate module BF_Switch(Pl,Pr,SPl,SPr,Clock,Ol,Or,SOl,SOr);
				BF_Switch #(k,x)	sw(.Pl(Datawires[x][2*w-2**x]),
											.Pr(Datawires[x][2*w]),
											.SPl(Stopwires[x+1][2*w-2**x]),
											.SPr(Stopwires[x+1][2*w-2**x+1]),
											.Clock(Clock),
											.Ol(Datawires[x+1][2*w-2**x]),
											.Or(Datawires[x+1][2*w-2**x+1]),
											.SOl(Stopwires[x][2*w-2**x]),
											.SOr(Stopwires[x][2*w])	);
			end
		end
	end
	endgenerate 
	
endmodule

`timescale 1ns / 1ps

module Scrambler(addr_in, Clock, func, addr_out);

	parameter k = 2;
	parameter io = 1;
	parameter addr_mm = k;
	parameter addr_line = 2*k;
	parameter data_size = k*k + k + 1; 	//include R\W BIT and Proccesor
	parameter p_size = k*k + 4*k + 1;

	input [p_size-1:0] 	addr_in;
	input 					Clock;
	input [3:0]				func; //16 possible funcs
	output [p_size-1:0] 	addr_out;
		
	reg [p_size-1:0] 	addr_out;
		
	//packet parts
	wire [data_size-1:0] data_part;
	wire [addr_mm-1:0] mm_part;
	wire [addr_line-1:0] line_part;
	
	assign mm_part 	= addr_in[p_size-1:data_size+addr_line];
	assign line_part 	= addr_in[data_size+addr_line-1:data_size];
	assign data_part 	= addr_in[data_size-1:0];
	
	always @ (posedge Clock) begin
  		  case (func)
			0: addr_out = addr_in;
			1: addr_out = {line_part,mm_part,data_part};
			2: addr_out = {~mm_part,~line_part,data_part};
			3: addr_out = {mm_part^2'b01,line_part,data_part};
			default: addr_out = addr_in;
		 endcase
	end
	
endmodule

module K_Bit_Scrambler(INPUTA,INPUTSA,Func_num,Clock,OUTPUTA,OUTPUTSA);
	parameter k = 2; // k == SIZE (2-> 2x2)
	parameter io = 1;
	parameter p_size = k*k + 4*k + 1;
	
	input [(2*k*p_size)-1:0] 	INPUTA;
	input [2*k-1:0]				INPUTSA;
	input [3:0] 					Func_num;
	input 							Clock;
	output [(2*k*p_size)-1:0] 	OUTPUTA;
	output [2*k-1:0]				OUTPUTSA;
	
	wire [(2*k*p_size)-1:0] 	OUTPUTA;// 	
	reg [2*k-1:0]					OUTPUTSA;;
	//wires for 2d arrays
	wire [p_size-1:0] 	INA 	[2*k-1:0];
		
	always @ (posedge Clock)
	begin
		OUTPUTSA = INPUTSA;
	end
			
	genvar a,d;
	generate for(a=0; a<2*k; a=a+1) begin:build_2d_array_1
		for(d=0; d<p_size; d=d+1) begin:build_2d_array_2
				assign INA[a][d] = INPUTA[d+(a*p_size)];
			end
			
		end
	endgenerate
		
	genvar x;
	generate for (x=0; x<2*k; x=x+1)  //genfor for creating first levels (straight)
		begin:Gen_scramblers	//gen module Scrambler(addr_in,addr_in_s, Clock, func, addr_out,addr_out_s);
			Scrambler #(k,io)	sw(.addr_in(INA[x]),
										.Clock(Clock),
										.func(Func_num),
										.addr_out(OUTPUTA[((x+1)*p_size)-1:x*p_size]));
		end
	endgenerate
	
	
	
endmodule

module BF_MM(In_p,clock,Out_P);
	parameter 	k = 2;
	parameter 	p_size = k*k + 4*k + 1;
	parameter 	Mod_size = k;
	parameter 	Intr_size = 2*k;
	parameter	Data_size = k*k;
	parameter 	Pr_size = k;
	
	input [p_size-1:0] In_p;
	input clock;
	output [p_size-1:0] Out_P ;

	reg [p_size-1:0] Out_P;
		
	//Memory Module Registers:
	reg [Data_size-1:0]	MM_Data [2*k-1:0];
	
	
	//packet parts declerations
	wire			[Pr_size-1:0]	Pr_Add;
	wire			[Mod_size-1:0]	MM_Add;
	wire			[Intr_size-1:0]	Intr_Add;
	wire							RW_flag;
	wire			[Data_size-1:0]	Data;
	
	//Break Packet to Parts:
	assign MM_Add		= In_p[p_size-1:Data_size+Intr_size+Pr_size+1];
	assign Intr_Add	= In_p[p_size-Mod_size-1:Data_size+Pr_size+1];
	assign RW_flag 	= In_p[Data_size+Pr_size];
	assign Data			= In_p[Data_size+Pr_size-1:Pr_size];
	assign Pr_Add		= In_p[Pr_size-1:0];
	
	always @ (posedge clock) 
	begin a:
		if (RW_flag==0) begin //Write Mode
			MM_Data[Intr_Add] = Data;
			Out_P = {Pr_Add,Intr_Add,RW_flag,Data,MM_Add};
		end
		else if (RW_flag==1) begin
			Out_P = {Pr_Add,Intr_Add,RW_flag,MM_Data[Intr_Add],MM_Add};
		end
	end
	
	
endmodule

module K_Bit_MM(INPUTA,INPUTSA,Clock,OUTPUTA,OUTPUTSA);
	parameter k = 2; // k == SIZE (2-> 2x2)
	parameter p_size = k*k + 4*k + 1;
	
	input [(2*k*p_size)-1:0] 	INPUTA;
	input [2*k-1:0] 				INPUTSA;
	input 							Clock;
	output [(2*k*p_size)-1:0] 	OUTPUTA;
	output [2*k-1:0] 			OUTPUTSA;
	
	wire [(2*k*p_size)-1:0] 	OUTPUTA;// 	
	reg [2*k-1:0] 			OUTPUTSA;// 	
	
	//wires for 2d arrays
	wire [p_size-1:0] 	INA 	[2*k-1:0];
	wire [p_size-1:0] 	OUTA 	[2*k-1:0];
		
	//Definitions of Internal wires
	wire [p_size-1:0]	WA	[2*k-1:0];
		
	always @ (posedge Clock)
	begin
		OUTPUTSA = INPUTSA;
	end
	
	genvar a,d;
	generate for(a=0; a<2*k; a=a+1) begin:build_2d_array_1
		for(d=0; d<p_size; d=d+1) begin:build_2d_array_2
				assign INA[a][d] = INPUTA[d+(a*p_size)];
				assign OUTPUTA[d+(a*p_size)] = OUTA[a][d];
		end
		assign OUTA[a]=WA[a];
	end
	endgenerate
	
	genvar x;
	generate for (x=0; x<2*k; x=x+1)  //genfor for creating first levels (straight)
		begin:Gen_MMs	//gen module BF_MM(In_p,In_OK,clock,Out_OK,Out_P);
			BF_MM #(k)		mm(.In_p(INA[x]),
									.clock(Clock),
									.Out_P(WA[x])	);
		end
	endgenerate
	
endmodule

module Main_module(INPUTA,INPUTSA,Func_num,Clock,OUTPUTA,OUTPUTSA);
	parameter k = 4; // k == SIZE (2-> 2x2)
	parameter levs = 3;
	parameter p_size = k*k + 4*k + 1;
	
	input [(2*k*p_size)-1:0] 	INPUTA;
	input [2*k-1:0]				INPUTSA;
	input [3:0] 					Func_num;
	input 							Clock;
	output [(2*k*p_size)-1:0] 	OUTPUTA;
	output [2*k-1:0] 				OUTPUTSA;
	
	wire [(2*k*p_size)-1:0] 	OUTPUTA;// 	
	wire [2*k-1:0] 				OUTPUTSA;
	
	//Definitions of Internal wires
	wire [(2*k*p_size)-1:0]			WA_0,WA_1,WA_2,WA_3,WA_4,WA_5; 	//interconnecting wires between modules
	wire [(2*k)-1:0]					WSA_0,WSA_1,WSA_2,WSA_3,WSA_4,WSA_5;
		
	assign WA_0 = INPUTA;
	assign WSA_0 = INPUTSA;
	assign OUTPUTA	=	WA_5;
	assign OUTPUTSA = WSA_5;
		
			
	genvar x;
	generate   //gen for creating first k-bit scrambler
		begin:Gen_scramblers_1	//gen module K_Bit_Scramber(INPUTA,INPUTSA,Func_num,Clock,OUTPUTA,OUTPUTSA);
			K_Bit_Scrambler #(k,1)	sw(.INPUTA(WA_0),
												.INPUTSA(WSA_1),
												.Func_num(Func_num),
												.Clock(Clock),
												.OUTPUTA(WA_1),
												.OUTPUTSA(WSA_5) );
		end
		begin:Gen_BF_NET_1	//gen module BF_Network(INPUTA,INPUTSA,Clock,OUTPUTA,OUTPUTSA);
			BF_Network #(k,levs)	sw(.INPUTA(WA_1),
											.INPUTSA(WSA_2),
											.Clock(Clock),
											.OUTPUTA(WA_2),
											.OUTPUTSA(WSA_1)	);
		end
		begin:Gen_MM	//gen module K_Bit_MM(INPUTA,INPUTSA,Clock,OUTPUTA,OUTPUTSA);
			K_Bit_MM	#(k)		sw(.INPUTA(WA_2),
										.INPUTSA(WSA_3),
										.Clock(Clock),
										.OUTPUTA(WA_3),	
										.OUTPUTSA(WSA_2) );
		end
		begin:Gen_BF_NET_2	//gen module BF_Network(INPUTA,INPUTSA,Clock,OUTPUTA,OUTPUTSA);
			BF_Network #(k,levs)		sw(.INPUTA(WA_3),
											.INPUTSA(WSA_4),
											.Clock(Clock),
											.OUTPUTA(WA_4),
											.OUTPUTSA(WSA_3)	);
		end
		begin:Gen_scramblers_2	//gen module K_Bit_Scramber(INPUTA,INPUTSA,Func_num,Clock,OUTPUTA,OUTPUTSA);
			K_Bit_Scrambler #(k,2)	sw(.INPUTA(WA_4),
												.INPUTSA(WSA_0),
												.Func_num(Func_num),
												.Clock(Clock),
												.OUTPUTA(WA_5),
												.OUTPUTSA(WSA_4)	);
		end
	endgenerate

	
endmodule