//MANUAL example of func() whose loop's body is perfectly covered by sub-graphs g1,g2,g3,g4
//int A[1024]={1,2,3,4};
//int func(int n)
//{
//int i;
//int x1,y1,a1,o1;
//int x2,y2,a2,o2;
//int x3,y3,a3,o3;
//int x4,y4,a4,o4;
//for(i=0;i<n;i++)
//{
//   /* g1: */ x1 = i-1; y1=n-i;        
//   /* g1: */ a1 = (A[x1-1]+y1)*y1;
//   /* g1: */ A[y1] = a1;
//   /* g1: */ o1 = (a1 - x1)*y1;
//
//   /* g2: */ x2 = n-1; y2=i-n;
//   /* g2: */ a2 = (A[x2-2]+y2)*y2;
//   /* g2: */ A[y2] = a2;
//   /* g2: */ o2 = (a2 - x2)*y2;
//
//   /* g3: */ x3 = o1-1; y3=o2-o1;
//   /* g3: */ a3 = (A[x3-3]+y3)*y3;
//   /* g3: */ A[y3] = a3;
//   /* g3: */ o3 = (a3 - x3)*y3;
//
//   /* g4: */ x4 = o2-1; y4=o1-o2;
//   /* g4: */ a4 = (A[x4-4]+y4)*y4;
//   /* g4: */ A[y4] = a4;
//   /* g4: */ o4 = (a4 - x4)*y4;
//}
//return(o4+o3);
//}


`define  W  31
`define M  1024
module dualram ( input [`W:0] data_x, data_y, input [`W:0] addr_x, addr_y, input we_x, we_y, clk, output reg [`W:0] q_x, q_y);
	reg [`W:0] ram[`M:0];
	always @ (posedge clk)
	begin if(we_x) begin ram[addr_x] <= data_x; end else q_x <= ram[addr_x]; end 
	always @ (posedge clk) begin if(we_y) begin ram[addr_y] <= data_y; end else q_y <= ram[addr_y]; end
endmodule

// fusing two dual port brams allowing at most two concurrent writes but upto four loads in parallel
// if there are writes they come in port_a and in port_b
module quadram ( input [`W:0] data_a, data_b, input [`W:0] addr_a, addr_b,addr_c, addr_d,
	input we_a, we_b, clk, output wire [`W:0] q_a, q_b,q_c, q_d);
wire [`W:0] addr_x, addr_y;
assign addr_x = (we_a)?addr_a : addr_c;
assign addr_y = (we_b)?addr_b : addr_d;
dualram mem1(data_a, data_b, addr_a, addr_b,we_a, we_b, clk, q_a, q_b);
dualram mem2(data_a, data_b, addr_x, addr_y,we_a, we_b, clk, q_c, q_d);
endmodule

module func(clk,reset,n,o);

input clk;
input reset;
input  wire [`W:0] n;
output wire [`W:0] o;

wire [`W:0] xu, yu, au, ou;
wire [`W:0] xv, yv, av, ov;
reg  [`W:0] RI;
reg  [`W:0] argu_i, argu_n, argv_i, argv_n;
reg  T;

wire [`W:0] data_a, data_b,data_c, data_d;
wire [`W:0] addr_a, addr_b,addr_c, addr_d;
wire       we_a, we_b;
wire  [`W:0] q_a, q_b,q_c, q_d;
//unit u
assign xu = argu_i-1; 
assign yu = argu_n-argu_i; 
assign addr_c = xu-1; 
assign au = (q_c + yu)*yu; 
assign ou = (au -xu)*yu;    
assign addr_a = yu; assign data_a = au; assign we_a = 1;
//unit v
assign xv = argv_i-1; 
assign yv = argv_n-argv_i; 
assign addr_d = xv-1; 
assign av = (q_d + yv)*yv; 
assign ov = (av -xv)*yv;    
assign addr_b = yv; assign data_b = av; assign we_b = 1;

assign o = ou + ov;

quadram mem(data_a, data_b, addr_a, addr_b,addr_c, addr_d, we_a, we_b, clk, q_a, q_b, q_c, q_d);

   always @(posedge clk)
   begin
    if(reset == 1) begin T <= 0; RI <= 0; argu_i <= 0; argu_n <= n; argv_i <= n; argv_n <= 0; end
    else 
    begin
      case (T)
      0: begin
         argu_i <= ou; argu_n <= ov; argv_i <= ov; argv_n <= ou;
         T <= 1;
         end
      1: begin
         argu_i <= RI; argu_n <= n; argv_i <= n; argv_n <= RI;
         if(RI < n) begin RI <= RI+1; T <= 0; end else begin T <= 1; end
         end
      endcase
    end
  end
endmodule

//proposed technique cover by [g1 || g2]; [g3 || g4]  73 lines of verilog
// Clock latency = 13ns
// #clock cycles per iteration = 2
//LUTs = 454 Registers = 97 Muxes = 0 Block_rams = 2 DSPs = 12 Power_dynamic = 0.048W

//Vivado HLS applied to func.c and the outcome verilog synthesized by Vivado 1869 lines of verilog code
// Clock latency = 6ns
// #clock cycles per iteration = 16
//LUTs = 854 Registers = 348 Muxes = 8 Block_rams = 1 DSPs = 18 Power_dynamic = 0.041W