Multi Port memory or Shared memory
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Structure
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R/W-ports ==> scrambel-unit ==> communication-network ==> memory-module

memory module- a regulare memory module adreses range from 0...k
scramble unit- translates an adress (A) from shared space to <module, inter-module>, 
communication- network

goal
-------

Simulate a shared memory space with adresses ranging 0...m*k. 

Features
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- variable number of ports and memory modules
- targets m memory modules that can be acessed concurently through n ports (special case m == n)

- read requests to the same cell are surved concurrently
- write requests to the same cell are surved concurrently

- read requests to diffrent cells in the same memory module are served
  sequentially. There are two options: block at port level or hold requests in
  buffers of 
- scramble unit uses universal hashing for psudo-random mapping


Possible structures
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* each module is acessed through
* pipeline mode of the communication network