/* Total Score= |0.0388445| */
/* Calculation Latency = |18.49| */
/* Max Gate Time= |1.849| */
/* Loop BB Percent = |0.735294| */
/* Gates Count = |35| */
module _Z11bouble_sortPii  (clk, reset, rdy,/* control */
	mem_out0, mem_in0, mem_addr0, mem_mode0, /* memport1 */
	mem_out1, mem_in1, mem_addr1, mem_mode1, /* memport2 */
	p_ar, i_n, return_value); /* params */
 input wire clk;
 input wire reset;
 output rdy;
 reg rdy;
 output [31:0] return_value;
 reg [31:0] return_value;
 input [15:0] p_ar;
 input [31:0] i_n;
input wire [31:0] mem_out0;
output reg [31:0] mem_in0;
output reg [15:0] mem_addr0;
output reg mem_mode0;
input wire [31:0] mem_out1;
output reg [31:0] mem_in1;
output reg [15:0] mem_addr1;
output reg mem_mode1;


 reg i_tmp136;   /*local var*/
 reg [31:0] i_i_01_0;   /*local var*/
 reg [15:0] p_tmp8;   /*local var*/
 reg [31:0] i_indvar_next14;   /*local var*/
 reg [31:0] i_tmp10;   /*local var*/
 reg i_tmp13;   /*local var*/
 reg [31:0] ltmp_0_1;   /*local var*/
 reg [31:0] i_indvar;   /*phi var*/
 reg [15:0] p_tmp20;   /*local var*/
 reg [31:0] i_tmp23;   /*local var*/
 reg [15:0] p_tmp25;   /*local var*/
 reg [31:0] i_tmp21;   /*local var*/
 reg [31:0] i_tmp26;   /*local var*/
 reg i_tmp27;   /*local var*/
 reg [31:0] i_j_07;   /*phi var*/
 reg i_tmp55;   /*local var*/
 reg [31:0] i_tmp60;   /*local var*/
 reg i_tmp64;   /*local var*/
 reg [31:0] i_tmp538;   /*local var*/
 reg i_tmp559;   /*local var*/
 reg [31:0] i_i_110;   /*phi var*/
 reg [31:0] i_tmp70;   /*local var*/

 /*Number of states:34*/
 reg [5:0] eip;
 `define entry0 6'd0
 `define entry1 6'd1
 `define bb0 6'd2
 `define bb1 6'd3
 `define bb2 6'd4
 `define bb3 6'd5
 `define bb4 6'd6
 `define bb5 6'd7
 `define bb6 6'd8
 `define bb7 6'd9
 `define bb8 6'd10
 `define bb9 6'd11
 `define bb170 6'd12
 `define bb171 6'd13
 `define bb172 6'd14
 `define bb173 6'd15
 `define bb174 6'd16
 `define bb175 6'd17
 `define bb300 6'd18
 `define bb301 6'd19
 `define bb302 6'd20
 `define bb480 6'd21
 `define bb481 6'd22
 `define bb580 6'd23
 `define bb581 6'd24
 `define bb582 6'd25
 `define bb61_preheader0 6'd26
 `define bb_nph120 6'd27
 `define bb_nph121 6'd28
 `define bb_nph122 6'd29
 `define bb51_preheader0 6'd30
 `define bb670 6'd31
 `define bb671 6'd32
 `define bb672 6'd33

/* Assign part (1)  */
wire [31:0] mul0_in_a;
wire [31:0] mul0_in_b;
 assign mul0_in_a = 
 (eip == `bb1) ? i_i_01_0 :0;
 assign mul0_in_b = 
 (eip == `bb1) ? (42) :0;

wire [31:0] out_mul0;
mul  mul0_instance (clk, mul0_in_a, mul0_in_b, out_mul0);



always @(posedge clk)
 begin
  if (reset)
   begin
    $display("@hard reset");
    eip<=0;
    rdy<=0;
   end

case (eip)
`entry0:
begin
	i_tmp136 <= (i_n > (0));
	eip <= `entry1;
end
`entry1:
begin
	if (i_tmp136) begin
		i_indvar <= (0);
		eip <= `bb0;
	end else begin
		eip <= `bb670;
	end
end
`bb0:
begin
	i_i_01_0 <= i_n-i_indvar;
	p_tmp8 <= p_ar + i_indvar;
	i_indvar_next14 <= i_indvar+(1);
	eip <= `bb1;
end
`bb1:
begin
	i_tmp10 <= i_i_01_0+(-1);
	eip <= `bb2;
end
`bb2:
begin
	i_tmp13 <= (i_tmp10 > (0));
	eip <= `bb3;
end
`bb3:
begin
	eip <= `bb4;
end
`bb4:
begin
	eip <= `bb5;
end
`bb5:
begin
	eip <= `bb6;
end
`bb6:
begin
	ltmp_0_1 <= out_mul0;
	eip <= `bb7;
end
`bb7:
begin
	mem_in0 <= ltmp_0_1;
	mem_mode0 <= 1;
	mem_addr0 <= p_tmp8;
	eip <= `bb8;
end
`bb8:
begin
	mem_mode0 <= 0;
	eip <= `bb9;
end
`bb9:
begin
	if (i_tmp13) begin
		i_indvar <= i_indvar_next14;
		eip <= `bb0;
	end else begin
		eip <= `bb61_preheader0;
	end
end
`bb170:
begin
	p_tmp20 <= p_ar + i_j_07;
	i_tmp23 <= i_j_07+(1);
	eip <= `bb171;
end
`bb171:
begin
	mem_mode0 <= 0;
	mem_addr0 <= p_tmp20;
	p_tmp25 <= p_ar + i_tmp23;
	eip <= `bb172;
end
`bb172:
begin
	i_tmp21 <= mem_out0;
	mem_mode1 <= 0;
	mem_addr1 <= p_tmp25;
	eip <= `bb173;
end
`bb173:
begin
	i_tmp26 <= mem_out1;
	eip <= `bb174;
end
`bb174:
begin
	i_tmp27 <= (i_tmp21 > i_tmp26);
	eip <= `bb175;
end
`bb175:
begin
	if (i_tmp27) begin
		eip <= `bb300;
	end else begin
		eip <= `bb480;
	end
end
`bb300:
begin
	mem_in0 <= i_tmp21;
	mem_mode0 <= 1;
	mem_addr0 <= p_tmp25;
	mem_in1 <= i_tmp26;
	mem_mode1 <= 1;
	mem_addr1 <= p_tmp20;
	eip <= `bb301;
end
`bb301:
begin
	mem_mode0 <= 0;
	mem_mode1 <= 0;
	eip <= `bb302;
end
`bb302:
begin
			eip <= `bb480;
end
`bb480:
begin
	i_tmp55 <= (i_tmp538 > i_tmp23);
	eip <= `bb481;
end
`bb481:
begin
	if (i_tmp55) begin
		i_j_07 <= i_tmp23;
		eip <= `bb170;
	end else begin
		eip <= `bb580;
	end
end
`bb580:
begin
	i_tmp60 <= i_i_110+(1);
	eip <= `bb581;
end
`bb581:
begin
	i_tmp64 <= (i_tmp60 < i_n);
	eip <= `bb582;
end
`bb582:
begin
	if (i_tmp64) begin
		i_i_110 <= i_tmp60;
		eip <= `bb51_preheader0;
	end else begin
		eip <= `bb670;
	end
end
`bb61_preheader0:
begin
	if (i_tmp136) begin
		eip <= `bb_nph120;
	end else begin
		eip <= `bb670;
	end
end
`bb_nph120:
begin
	i_tmp538 <= i_n+(-1);
	eip <= `bb_nph121;
end
`bb_nph121:
begin
	i_tmp559 <= (i_tmp538 > (0));
	eip <= `bb_nph122;
end
`bb_nph122:
begin
	if (i_tmp559) begin
		i_i_110 <= (0);
		eip <= `bb51_preheader0;
	end else begin
		eip <= `bb670;
	end
end
`bb51_preheader0:
begin
			i_j_07 <= (0);
		eip <= `bb170;
end
`bb670:
begin
	mem_mode0 <= 0;
	mem_addr0 <= p_ar;
	eip <= `bb671;
end
`bb671:
begin
	i_tmp70 <= mem_out0;
	eip <= `bb672;
end
`bb672:
begin
	 rdy <= 1;
 return_value <= i_tmp70;
 $display("Return (%d) ",i_tmp70);
 $finish();
end
 endcase //eip
end //always @(..)

endmodule


 // Test Bench 


module _Z11bouble_sortPii_test;
 wire rdy;
 reg reset, clk;
wire [31:0] mem_out0;
wire [31:0] mem_in0;
wire [15:0] mem_addr0;
wire mem_mode0;
wire [31:0] mem_out1;
wire [31:0] mem_in1;
wire [15:0] mem_addr1;
wire mem_mode1;
xram r1 (mem_out0, mem_in0, mem_addr0, mem_mode0, clk,
        mem_out1, mem_in1, mem_addr1, mem_mode1, clk);


 always #5 clk = ~clk;
 reg [15:0] p_ar;
 reg [31:0] i_n;
 wire [31:0] return_value;
_Z11bouble_sortPii instance1 (clk, reset, rdy,/* control */
	mem_out0, mem_in0, mem_addr0, mem_mode0, /* memport1 */
	mem_out1, mem_in1, mem_addr1, mem_mode1, /* memport2 */
	p_ar, i_n, return_value); /* params */
initial begin
 clk = 0;
 $monitor("return = %b, %d", rdy,  return_value);
 p_ar <= 0;
 i_n <= 0;
 #1 reset = 1; #1 reset = 0;
 #1 reset = 1; #1 reset = 0;
 #1 reset = 1; #1 reset = 0;
end

endmodule //main_test