Dr. Gadi Haber
|
Mailing address |
Matam
Haifa |
|
|
Office Phone |
+972-4-8153274 |
|
|
|
|
|
|
|
|
Teaching at the Technion Institute
Student guidance at the University of Haifa
Chairing at International Conferences
Academic degrees
2002
P.hd. in Mathematics and Computer Science, Haifa University.
1995
M.Sc. in Computer Science, Hebrew University.
1992
B.Sc. in Physics and Computer Science, Hebrew University.
Research interests
·
Distributed Denial-of-Service (DDoS) protection
·
Parallel algorithms
·
Source-level compilation
· Binary
Translation and post-link optimizations
Teaching at the Technion Institute
·
Course id 04625 on Binary-Level Translation and Optimizations course at the EE department.
Student guidance at the University of Haifa
· Projects
Guidance
- OCA - Optimizing Code Advisor – Eclipse plugin tool for recommending and guiding optimizations at source level:
- OCA homepage: http://www.optca.org
- LibTune - a tool for optimizing library function calls within executable files using Intel Pin tool.
- Msc
and Phd Thesis Guidance
- Compilation projects for CPU Firmware microcode using the LLVM framework Skeletonization.
- Source-level parallelization recommendations using code Skeletonization.
- Resolving conflicts between pairs of run-time optimizations.
- Flow graph algorithms for complementing partial edge profile.
- Source-level Object Inlining optimization in Java programs.
Chairing at
International Conferences
Program chair at
the Compiler, Architecture and Tools conferences (CATC)
The focus of the Compiler, Architecture and Tools conferences (CATC) is on advanced compiler and architecture technologies ranging from static to dynamic and binary translation, for modern processor architectures and associated tools.
This year's CATC event: CATC 2021 homepage
Past CATC events: CATC 2019, CATC 2018, CATC 2017, CATC 2016, CATC 2015, CATC 2014, CATC 2013,
General Chair SYSTOR 2010
conference Intel
Development Center haifa, Israel 2017 - today Senior Software
Compilation Architect at the Intel Core Group. 2017 - 2018 Senior Software
Architect at the Compiler Group. 2016 Senior Software
Architect at the Binary Instrumentation and Translation Group. 2011 – 2015 Manager of the
Binary Translation Group. The
Technion Institute 2016 - today Adjunct lecturer of the course Binary-Level
Translation and Optimizations in the Electrical Engineering Faculty at the Technion, Haifa. The
University of Haifa 2003 - today External instructor of graduate
and under graduate students in the areas of compilation, parallel computing and
source-level optimizations in the Computer Science Department at the Haifa
University. Ort
Braude College 2011 – 2012 External lecturer for under
graduate students in Information Analysis course. IBM
Research lab. in Haifa 2008 – 2011 Founder and team lead of the “Performance
Quality and Services (PQS)” team that provides rescuing, performance and
quality services for large projects. Involved in the design and
promotion of IBM Performance tools for multicore development, such as IBM
VPA (Visual Performance Analyzer) – a visualization tool for performance
analysis and debugging of programs running on IBM multicore platforms. Provides direct consultancy and
support to IBM customers for the IBM platforms. 2007 - 2008 Senior Architect on Performance
Analysis and Optimizations on one year assignment at the IBM labs in Austin
Texas. 2005 - 2007 Manager of "Performance
Analysis and Optimization Technologies (PAOT)" group at IBM
Research Lab in Haifa which focuses on research and development of IBM
post-link technology. The post-link technology consists
of the following tools: ·
FDPR-Pro
(Feedback Directed Program Restructuring) – a post-link profile-based
optimization tool that operates directly on executable files or libraries. ·
BProber – advanced binary probing utility for
instrumenting given executable files. ·
Code
Analyzer – an eclipse visualization plugin which provides performance
analysis for executable files. 2004 - 2005 Senior architect of the IBM Haifa
Research Lab activities in post-link technologies. 1997 - 2004 Project leader at IBM Haifa
Research Lab, in the area of optimizations on binary program files. 1993 - 1996 Research staff member at IBM
Research Lab in Haifa. Articles in refereed conferences and workshop
proceedings Gadi Haber,
Shachaf Altman, Behnaz Ghouchani, Intel C Compiler for the Intel® Core™ Microarchitecture Code, CATC 2019 - Compilers
Architecture and Tools conference, Haifa Israel, December 16, 2019.
Gadi Haber, Coby Tayree, Intel Haifa
Development Center, Israel CATC 2017 - Compilers
Architecture and Tools conference, Haifa Israel, December 4, 2017. A Study of
Conflicting Pairs of Compiler Optimizations, Cfir Aguston, Yosi Ben Asher,
Gadi Haber OCA (Optimizing
Code Advisor) - Tool for OpenMP
Recommendations, CATC 2016 - Compilers,
Architecture and Tools Conference, Haifa Israel September 15, 2016. Yosi Ben Asher, Gadi Haber,
Yacov Gendel, Oren Segal and Yousef Shajrawi A study of manycore shared Memory Architecture as a way to
build SOC applications, SpringSim 2015: Spring
Simulation Multi-Conference, Alexandria, VA, USA, April 12 - 15, 2015. Yosi Ben-Asher, Gadi Haber and
Yousef Shajrawi A Study on
Conflicting Pairs of Compiler Optimizations, CATC 2014: Compiler,
Architecture and Tools conference, Haifa, Israel, December 1, 2014. Y. Ben Asher, J. Gendel, G.
Haber, O. Segal, Y. Shajrawi 1K Manycore FPGA Shared Memory
Architecture for SOC FPGA 2014: The
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 26 - 28, 2014. CATC 2013: Compiler,
Architecture and Tools conference, Haifa, Israel, April 22, 2014 C. Aguston, Y. Ben Asher and
G. Haber Parallelization Hints via Code Skeletonization CATC 2012: Compiler,
Architecture and Tools conference, Haifa, Israel, November 26, 2012. Y. Ben-Asher, T.
Gal, G. Haber, M. Zalmanovici Refactoring techniques
for aggressive object inlining in java applications Automated
Software Engineering (AUSE) journal Volume 19,
Number 1, pages 97-13 DOI: 10.1007/s10515-011-0096-x (2012) Y. Ben Asher, E. Fisher, G.
Haber and V. Tartakovski Fast Evaluation of Boolean
Circuits Based on Two-Players Game and Optical Connectivity Circuits, The 41st International
Conference on Parallel Processing (ICPP 2012), Pittsburgh, PA, September 10-13,
2012. Y. Ben-Asher, D. Giver, G.
Haber, G. Kulish, HparC: A Mixed Nested Shared Memory and Message Passing
Programming Style Intended for Grid G. Haber, I. Newman
and R. Levin, Y. Ben-Asher, D.
Citron, O. Boehm, G. Haber, M. Klausner, R. Levin, Y. Shajrawi E. Farchi, M. Klausner, S. Fienblit,
Y. Filiarsky, S. Gammer, G.
Haber, S. Novikov, N. Peleg, O. Raz D. Citron, G. Haber
and R. Levin, G. Haber, M.
Klausner, V. Eisenberg, B. Mendelson, M. Gurevich, G. Haber, M.
Klausner, B. Mendelson and V. Eisenberg, G. Haber, E. A. Henis and V. Eisenberg, E. A. Henis, G. Haber, M. Klausner and A. Warshavsky,
Y. Ben-Asher and G.
Haber, Y. Ben-Asher and G.
Haber, Y. Ben-Asher and G.
Haber, Cfir Aguston,
Yosi Ben-Asher, Gadi Haber Parallelization
Hints via Code Skeletonization IEEE
Transactions Parallel Distributed Systems Volume 26(11):
3099-3107, 2015 Y. Ben-Asher, T.
Gal, G. Haber, M. Zalmanovici Refactoring
techniques for aggressive object inlining in java
applications Automated
Software Engineering (AUSE) journal Volume 19,
Number 1, pages 97-13 DOI: 10.1007/s10515-011-0096-x (2012) R. Levin, I. Newman
and G. Haber, Y. Ben-Asher, D.
Citron and G. Haber, Y. Ben-Asher and
G. Haber, G. Haber, Y.
Ben-Asher, ISCA 2013
Tutorial on Analysis Methodologies and Tools, Tel-Aviv, Israel, June 23 Introduction
to Binary Translation ISCA 2013
AMAS-BT - 6 th Workshop on
Architectural and Microarchitectural Support for
Binary Translation workshop, June 23. Speculative CMOVcc hardware instruction.
Filed patent AA5732-US
BRANCH PREDICTOR WITH BRANCH RESOLUTION CODE INJECTION.
U.S. Patent Application File No. 081903.0600 (Intel File No. P109190US)
New Vector Instruction Set Supporting Operations with Constant Values.
Intel File No. 144239
Core switching
acceleration in asymmetric multiprocessor system. Patent number 93485945 Method and
apparatus for performance efficient ISA virtualization using dynamic partial
binary translation. Patent number 9250906 Systems,
methods and apparatuses for improving performance of status dependent
computations. Filing number US/16172343.2-1957,
2015 An
acceleration of core switching mechanism for asymmetric multi
processor system, based on binary analysis and code instrumentation Filing number 13/992,710,
2013 Using Binary
Translation to bridge over ISA differences in an asymmetric multiprocessor
system Filed patent
#86521, 2013 G.Haber, M. Zalmanovici Efficient Data
Profiling to Optimize System Performance Filing Date:
April 4, 2011 IBM Disclosure
number: IL9-2011-0002 G.Haber, Performance
Assessment of a Program Model Filing Date:
March 21, 2011 IBM Disclosure
number: IL9-2010-0129 IBM Docket
number: IL9-2010-0129US1 G.Haber, O. Boehm, Y. Shajrawi Optimizing
Program Code Using Branch Elimination Filing Date:
September 30, 2009 IBM Disclosure
number: IL8-2008-0475 IBM Docket
number: IL9-2010-0059 G.Haber, O. Boehm, Y. Shajrawi Optimizing
Program Code Using Branch Elimination Filing Date:
September 30, 2009 IBM Disclosure
number: IL8-2008-0475 IBM Docket
number: IL9-2009-0059 G. Haber, D.
Citron Load Time
Optimization Tool Filing Date:
February 3, 2009 IBM Disclosure
number: IL8-2008-0418 IBM Docket
number: IL9-2009-0008. G. Haber, Y. Yaari, M. Zalmanovici Iterative
Compilation Supporting Entity Instance-Specific Compiler Option Variations Filing Date:
January 28, 2008 IBM Disclosure
number: IL8-2007-0097 IBM Docket
number: IL9-2007-0079. G. Bashkansky,
G. Haber, M. Zalmanovici Device,
System, and Method of Computer Program Optimization Filing Date: IBM Disclosure
number: IL8-2007-0018 IBM Docket
number: IL9-2007-0047. G. Haber, R. Levin, S.Ur Method for
Enabling Profile-Based Call Site Tailoring Using Profile Gathering of Cloned
Functions Filing Date: IBM Disclosure
number: IL8-2007-0038 IBM Docket
number: IL9-2007-0040. G. Haber, R.
Levin, M. Gurevich, G. Haber, A. Heilper, A. Landau Improving the Operation of Relational Database Optimizers
by Inserting Redundant Sub-Queries in Complex Queries IBM Disclosure number IL8-2006-0025 IBM Docket number IL9-2006-0040 Filed on June 27, 2006. G. Haber, A. Heilper, M. Zalmanovici IBM Disclosure number IL8-2005-0146 IBM Docket number
IL9-2006-0033 Filed on June 11, 2006 G. Haber, M. Klausner, V. Eisenberg, Percolating hot
function store/restores to colder calling functions U.S Patent number 7036116 Issued April 25, 2006 G. Haber, M. Klausner, V. Eisenberg Eliminating Cold Register Stores/Restores Within Hot
Function Prologs/Epilogs, U.S Patent
number 7,017,154 Issued March 21, 2006 G. Haber, M. Klausner, V. Eisenberg, Eliminating Stores/Restores Within Hot Function Prologs/Epilogs
Using Volatile Registers, U.S. Patent number 7,017,154, Issued 21/03/2006 G. Haber, M. Klausner, V. Eisenberg, Optimizing Post-Link Code, U.S. Patent number 6,966,055, Issued 11/2005 G. Haber, M. Zalmanovici, Profiling of Performance Behaviour
of executed Loops, Filed on November 2005. I. Goldberg, G. Haber, Method and System for Enhancing E-mail Correspondence, Filed on October 2005. G. Haber, R. Levin,
D. Citron, A Link-time Profile Based Method for Reducing Run-time
Image of Executables, IBM Disclosure number IL8-2003-0070, IBM Docket number IL9-2004-0021, Filed on Aug. 27, 2004. G. Haber, M. Klausner, V. Eisenberg,
M. Gurevich, A Feedback Directed Method for Optimizing the Program's
Code using Global Data Reordering at Link-time, IBM Disclosure number IL8-2002-0028, IBM Docket number IL9-2002-0024, Filed on Dec. 31, 2002. J. Civlin, G. Haber, B. Mendelson, D.
Bernstein, I. Nahshon, Method and Storage Medium for Building Very Large
Executable Programs, U.S. Patent number 6,145,125, Issued Nov. 7, 2000.
SYSTOR conferences aim at promoting systems research and foster stronger ties
between the Israeli and worldwide systems research communities and industry.
In 2010 the conference was held in
See conference site at: https://www.research.ibm.com/haifa/conferences/systor2010/index.shtmlEmployment history
Senior architect for the "Code Optimization Technology and Quality
(COQT)" department at the IBM Research lab in Haifa.Publications
IEEE
Trans. Parallel Distrib. Syst. 26(11): 3099-3107, 2015 (TPDS). O. Boehm, G. Haber, H. Kosachevsky,
Code Alignment for Architectures
with Pipeline Group Dispatching
3rd Annual Haifa Experimental
Systems Conference (SYSTOR 2010),
Haifa Israel, May 24-26, 2010, ACM ICPS proceedings of SYSTOR’10
3rd Annual
D. Vianney,
G. Haber, A. Heilper, M. Zalmanovici,
Performance Analysis and Visualization Tools for
Cell/B.E. Multicore Environment
First International Forum on
Next-Generation Multicore/Manycore Technologies,
Complementing Missing and Inaccurate Profiling
using a Minimum Cost Circulation Algorithm
2008 International Conference on High
Performance Embedded Architectures & Compilers (HiPEAC
2008),
Göteborg, SWEDEN, January 27-29, 2008.
Aggressive Function Inlining:
Preventing Loop Blockings in the Instruction Cache
2008 International Conference on
High Performance Embedded Architectures & Compilers (HiPEAC
2008),
Göteborg, SWEDEN, January 27-29, 2008.
The Advantages of Post-link Code Coverage
Third Annual Haifa Verification Conference (HVC 2007),
Haifa, Israel, October 23 – 25, 2007
Reducing Program Image Size by Extracing Frozen
Code and Data
Fourth ACM International Conference on Embedded Software (EMSOFT 2004),
Pisa, Italy, September 27-29, 2004.
Y. Ben-Asher, D. Citorn and G. Haber,
Overlapping Memory Operations with Circuit Evaluation in Reconfigurable
Computing
11th Reconfigurable Architectures Workshop (RAW 2004),
Optimization Opportunities Created by Global Data Reordering
First International Symposium on Code Generation and Optimization (CGO
2003),
San Francisco, California, pp. 228-241, March, 2003.
Light Weight Optimization for Reducing Hot Saves and Restores of Callee-Saved Registers,
Fourth Workshop on Feedback-Directed and Dynamic Optimization
(FDDO 2001), Austin Texas, December 2, 2001.
Reliable Post-link Optimizations Based on Partial Information,
Third Workshop on Feedback-Directed and Dynamic Optimization
(FDDO 2000),
Feedback Based Post-link Optimization for Large Subsystems,
Second Workshop on Feedback-Directed Optimization (FDO'99),
Haifa Israel, pp. 13-20, November 1999.
Efficient Parallel Solutions of Indexed Recurrences with Linear Combinations,
SPAA'99 conference, Saint-Malo France, pp. 212-221, June 1999.
Parallel Solutions to a Simple Class of Indexed Recurrences,
EuroPar'98 conference, Southampton England, pp. 933-939, September 1998.
Parallel Solutions of Indexed Recurrence Equations,
IPPS'97 conference, Geneva Switzerland, pp. 413-427, April 1997.
Y. Ben-Asher and G. Haber,
On the Usage of simulators to detect inefficiency of
parallel programs caused by "bad" schedulings:
the SIMPARC approach,
HiPC'95 (High performance
computing),
Articles in refereed journals
Complementing Missing and Inaccurate Profiling Using a Minimum Cost
Circulation Algorithm,
High Performance Embedded Architectures and Compilers (HiPEAC) , Vol. 4917, 2008,
pp. 291-304
Overlapping Memory Operations with Circuit Evaluation in Reconfigurable
Computing,
International Journal of Embedded Systems (IJES) , Vol. 2, Nos. 1/2, 2006
pp. 16-27
Y. Ben-Asher and G. Haber,
Efficient Parallel Solutions of Linear Algebraic Circuits,
Journal of Parallel and Distributed Computing (JPDC), vol. 64, 2004, pp.
163-172
Parallel Solutions of Simple Indexed Recurrence Equations,
IEEE transactions on Parallel and Distributed Systems, January 2001, volume
12, number 1, pp. 22-37.
On the Usage of simulators to detect inefficiency of parallel programs
caused by "bad" schedulings: the SIMPARC
approach,
Journal of Systems and Software (JSS) Volume 33, Number 3, June 1996, pp.
313-327.
Published Tutorials
G. Haber,
Chapter 4. Code Analyzer,
"IBM Visual Performance Analyzer User Guide",
http://dl.alphaworks.ibm.com/technologies/vpa/vpa.pdfG.
Haber
Tutorial - Performance Tools for Understanding the
Behavior of Multicore Programs
Tutorial in the third Israeli Workshop on Multicore
(CMP III), Technion, Israel, Feb.
3, 2009,
presented coding
examples: http://sysrun.haifa.il.ibm.com/hrl/euler_example_for_cell
presented foils: http://workshop.ee.technion.ac.il/upload/Events/CMP/Haber.pdfG.
Haber, B. Mendelson, T. Chen,
Performance Tools for Understanding the
Behavior of Running Programs on the Cell B.E.,
Tutorial in the 41st International Symposium on Microarchitecture (Micro 41),
http://sysrun.haifa.il.ibm.com/hrl/micro-41-2008/
presented foils: http://sysrun.haifa.il.ibm.com/hrl/micro-41-2008/present/micro41_cell_tools_tutorial_4.pdf
G.
Haber,
Cell Broadband Engine SDK 3.0 tools, Part
1: Using performance tools,
published on IBM developerWorks,
http://www.ibm.com/developerworks/edu/pa-dw-pa-sdk3tool.htmlG. Haber,
Chapter 6. Using Performance Tools,
IBM Redbook on "Programming the Cell Broadband
Engine: Examples and Best Practices",
http://www.redbooks.ibm.com/abstracts/sg247575.htmlPatents
Method for presenting machine instructions in a machine-independent tree
form suitable for post-link optimizations,
IBM Disclosure number: IL9-2006-0086,
Filed on December 5, 2006.Method for
code personification using program scrambling